As one of duplex technologies, TDD will allow uplink and downlink to share a same frequency band in different time, and thus it requires a periodical fast switching between the uplink and the downlink in time domain so as to realize the duplex. FIG. 1 schematically illustrates a switching between the downlink and the uplink in a TDD system in prior art. As illustrated, an uplink time slot 110 and a downlink time slot 130 will utilize the same frequency band source in different time slots and there is further provided a Guard Period (GP) 120 between the uplink time slot 110 and the downlink time slot 130 to provide a protection in switching.
In a periodical fast switching system in time domain such as a TDD system, to improve a linearity of power amplifier (PA) that is used to amplify the RF signal to be transmitted, nonlinearity correction is widely used. As a typical means of nonlinearity correction, a Digital Pre-distortion (DPD) technology is well-known. The DPD technology enables the PA to trade linearity for efficiency so as to obtain significant power saving, and it has become an important part in modern communication systems.
FIG. 2 schematically illustrates a typical structure of a power amplifier system for using in a TDD system wherein the power amplifier is capable of utilizing nonlinearity correction. As illustrated in FIG. 2, a DPD module 201, which may be implemented by a FGPA, ASIC, etc., performs a DPD correction on an input signal, the signal output from the DPD module 201 will be sent to a Digital to Analog Converter (DAC) 202, which in turn converts digital signal into analog signal. Then, the analog signal will be input into the TX (low level) module 203 so as to convert the base-band signal to an RF signal, the PA 204 will then amplify the RF signal. After that, the amplified signal will be further guided to a filter unit (FU) via a circulator 207 and transmitted via antenna (not shown). On the other hand, the output of the PA is further fed back to the DPD module for using in DPD correction. Specifically, the output of PA is down-converted through a feedback (low level) module 205 and is converted into a digital signal by an Analog to Digital Converter (ADC) 206; the digital feedback signal then will be provided to the DPD module 201, which will calculate the distortion coefficients based on these feedback signals so as to perform DPD correction. Similarly, for receiving side, a signal received by antenna will be filtered by the FU and transmitted to a Low Noise Amplifier (LNA) 208 via circulator 207, and then the amplified signal will be further sent to a receiving portion (RX) for further processing.
Different from frequency division duplex (FDD) system, the TDD system will turn off a quiescent bias voltage of the PA during the uplink time slot so as to further save power and minimize receiver noise, which has become a common means in the TDD system. FIG. 3 schematically illustrates a bias control scheme of a power amplifier in the prior art, wherein it is assumed that the power amplifier comprises a Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor or an enhancement type transistor. As illustrated, during an uplink time slot, a voltage provided to a gate bias terminal of the PA is set as zero while the voltage is set as a normal bias voltage (i.e., a voltage that causes the transistor in the PA in a biasing condition so as to amplify the input signal as designed) during a downlink time slot. Additionally, there is further provided a protection time before the downlink time slot begins, which means the normal bias voltage has been provided in advance prior to the downlink time slot so as to ensure that the quiescent bias voltage of a power transistor is well turned on when the downlink data comes. However, due to turning off and on the quiescent bias voltage, it may be observed that the linearity performance of the PA changes considerably.
Furthermore, US patent application publication No. 2012/0286866A1 titled “AMPLIFIER PERFORMANCE STABILIZATION THROUGH PREPARATORY PHASE” discloses a method and related systems for amplifier performance stabilization of a digitally pre-distorted RF power amplifier to tackle digital pre-distortion problems during an initial application of an RF signal to a power amplifier or in a PA-DPD's start up process. Before the RF signal is applied to the power amplifier and the digital pre-distortion calculation starts, there is provided a preparatory phase in which a quiescent current of the power amplifier will be increased to a high level beyond nominal values when the operating temperature is less than a predetermined temperature in order to rapidly warm up the completely cold PA.
However, during switching from the uplink time slot to the downlink time slot, it still may observe a notable deterioration in the DPD linearization performance of the PA. This lies in that update rate of the DPD module can not yet match characteristics changes of a transistor in the PA which are resulted from turning off and on the quiescent bias voltages of the PA. In other word, calculated DPD coefficients are not suitable for input signals and the linear relationship of the PA is lost. Therefore, Adjacent Channel Leakage Ratio (ACLR), which may represent the DPD linearization performance of the PA, might be deteriorated remarkably.
Reference is made to FIGS. 4A-4E. FIG. 4A schematically illustrates ACLR values in different frequency ranges at beginning of a first downlink subframe. A frequency range of desired signals is located centrally and has an ACLR value of 46.0 dBm; two frequency ranges lower than the frequency range of desired signals are illustrated located at left side and have ACLR values of −65.8 dBc and −51.8 dBc respectively; and two frequency ranges higher than the frequency range of desired signals are illustrated at right side and respectively have ACLR values of −49.9 dBc and −65.9 dBc. Particularly, ACLR values in the frequency ranges immediately adjacent to the frequency range of desired signals are highlighted by black blocks. FIG. 4B schematically illustrates corresponding signal portion in the first downlink subframe on which the ACLR values as illustrated in FIG. 4A are tested, from which it is clear that it is at beginning of the first downlink subframe after an uplink time slot. FIG. 4C schematically illustrates ACLR values in different frequency ranges at beginning of a third downlink subframe, the frequency ranges are similar to those illustrated in FIG. 4A and respectively have ACLR values of −66.0 dBc, −60.4 dBc, 46 dBm, −58.3 dBc and −65.6 dBc. Moreover, ACLR values in the frequency ranges immediately adjacent to the frequency range of desired signals are also highlighted by black blocks. Similarly, FIG. 4D schematically illustrates corresponding signal portion in the third downlink subframe on which the ACLR values as illustrated in FIG. 4C are tested, and it is clear that it is at beginning of the third downlink subframe.
Besides, FIG. 4E schematically further illustrates a comparison between ACLR values in frequency ranges immediately adjacent to the frequency range of desired signals in the first downlink subframe and in the third downlink subframe, wherein the ACLR values to be compared have been highlighted by black blocks in both FIGS. 4A and 4C. From FIG. 4E, it is clear that, compared to the beginning of the third downlink subframe which may represent a steady status in the downlink time slot (i.e., a status in which both a thermal balance and an electric balance are achieved), the ACLR deteriorates about 8 dB at the beginning of the first downlink subframe (i.e., when the PA is just turned on), and specifically, 8.6 dBc in a lower frequency range and 8.4 dBc in an upper frequency range respectively. This clearly reflects that, in the periodical fast switching system in time domain such as a TDD system, the linearity performance of the PA is degraded at beginning of a downlink time slot.